Programming/Verilog(A)/SVerilog
메모리에서 특정 비트만 읽기
stluck
2009. 5. 12. 12:53
chi = mem[raddr][bitplane]; synthesis X
wire [bitwidth:0] chi_t; synthesis O
assign chi_t = mem[raddr];
assign chi = chi_t[bitplane];
wire [bitwidth:0] chi_t; synthesis O
assign chi_t = mem[raddr];
assign chi = chi_t[bitplane];